This invention relates to the storage of high speed digital information and more particularly to processing of this information prior to storage so as to reduce the complexity of known storage systems.
When an analogue video signal for example is converted into digital form, it is commonly found that digital storage is used prior to reconversion of the signal to analogue form. Such conversion and storage is used for example in digital time base correctors (see for example U.S. Pat. Nos. 3,978,519 and 3,860,952). To control the flow of digital information into and out of storage devices, store clock pulses are needed. Suitable storage devices could comprise digital shift registers. The rate at which storage devices can handle data is limited and often falls short of the rate at which the video data is flowing. An example of this is in the processing of television signals where the information rate is much higher than the clock rate of available storage devices. A well established technique known as demultiplexing is used to effectively reduce the data rate by diverting information arriving serially to a number of parallel storage paths. If every piece of information is allocated to one of n parallel storage paths, then the information rate seen by the storage devices is one nth of the incoming serial information rate. Each storage path must, therefore, be supplied with clock pulses at one nth of the input serial data rate but staggered in time one to another by periods equal to the period of the serial data. This implies n phases of store clock pulses. In many television systems a multiplicity of storage devices may be used to provide the necessary store capacity, and the number of components needed to provide the multiple phases of clock drives becomes highly significant.